94 research outputs found
06141 Abstracts Collection -- Dynamically Reconfigurable Architectures
From 02.04.06 to 07.04.06, the Dagstuhl Seminar 06141 ``Dynamically Reconfigurable Architectures\u27\u27 was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl.
During the seminar, several participants presented their current
research, and ongoing work and open problems were discussed. Abstracts of
the presentations given during the seminar as well as abstracts of
seminar results and ideas are put together in this paper. The first section
describes the seminar topics and goals in general.
Links to extended abstracts or full papers are provided, if available
10281 Abstracts Collection -- Dynamically Reconfigurable Architectures
From 11.07.10 to 16.07.10, Dagstuhl Seminar 10281 ``Dynamically Reconfigurable Architectures \u27\u27 was held
in Schloss Dagstuhl~--~Leibniz Center for Informatics.
During the seminar, several participants presented their current
research, and ongoing work and open problems were discussed. Abstracts of
the presentations given during the seminar as well as abstracts of
seminar results and ideas are put together in this paper. The first section
describes the seminar topics and goals in general.
Links to extended abstracts or full papers are provided, if available
RapidRadio: A Domain-Specific Productivity Enhancing Framework
The RapidRadio framework for signal
classification and receiver deployment is discussed. The framework
is a productivity enhancing tool that reduces the required
knowledge-base for implementing a receiver on an FPGA-based
SDR platform. The ultimate objective of this framework is to
identify unknown signals and to build FPGA-based receivers
capable of receiving them. The architecture of the receiver
deployed by the framework and its implementation are discussed.
The framework's capacity to classify a signal and deploy a
functional receiver is validated with over-the-air experiments
The (empty?) Promise of FPGA Supercomputing
There have been some notable success stories in the past that give merit to the viability of the creation of an FPGA-based supercomputer. When examining the computing potential of these devices, they appear to offer competitive computational characteristics that are highly competitive to contemporary high-performance processors. Recently, there have been supercomputer-class processing blades offered by the leading high-performance computing specialist, yet the sales of these nodes have been less than spectacular. This talk examines why this may be the case, and explores the viability and cost-performance of FPGA-based supercomputers
Dynamic Hardware Development
Applications that leverage the dynamic partial reconfigurability of modern FPGAs are
few, owing in large part to the lack of suitable tools and techniques to create them. While
the trend in digital design is towards higher levels of design abstractions, forgoing hardware
description languages in some cases for high-level languages, the development of a reconfigurable
design requires developers to work at a low level and contend with many poorly
documented architecture-specific aspects. This paper discusses the creation of a high-level
development environment for reconfigurable designs that leverage an existing high-level synthesis
tool to enable the design, simulation, and implementation of dynamically reconfigurable
hardware solely from a specification written in C. Unlike previous attempts, this approach
encompasses the entirety of design and implementation, enables self-re-configuration
through an embedded controller, and inherently handles partial reconfiguration. Benchmarking
numbers are provided, which validate the productivity enhancements this approach
provides
Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA
(OFDM) can provide a flexible usage of the spectrum by controlling individual subcarriers. Sets of subcarriers can be zero-modulated to avoid interfering narrowband primary users, making OFDM a strong candidate for Cognitive Radio implementations. This paper presents the design and implementation of a non-contiguous OFDM physical layer (PHY) capable of supporting arbitrary allocation vectors and spectrum sensing for cognitive radio applications. Least squares methods applied on an arbitrary set of pilot subcarriers are used to estimate and track the phase errors caused by residual carrier frequency offset and by non-ideal sampling frequency at the receiver. A full FPGA prototype was developed and evaluated using Virtex-4 devices, including over-the-air testing in the 2.05 GHz radio band
14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 9-11 June 2003, San Diego, CA, USA
International audienc
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